Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC*Supported by National Natural Science Foundation of China (11375100), Strategic Pioneer Program on Space Sciences, Chinese Academy of Sciences (XDA04060606-06) and State Key Laboratory of Particle Detection and Electronics. (July 2016)

• Record Type: Journal Article
• Authors: Zhang 章, Hong-Yan 洪燕; Deng 邓, Zhi 智; Liu 刘, Yi-Nong 以农
• Is Part Of: Chinese physics C. Volume 40:Number 7(2016:Jul.)
• Publication Date: 2016-07
• Subjects: 84.30.-r -- 29.40.Gx; MOS capacitor -- non-ideal effects -- waveform recorder -- switched capacitor array -- ASIC; Particles (Nuclear physics) -- Periodicals; Nuclear physics -- Periodicals; 539.76
• DOI: 10.1088/1674-1137/40/7/076102
• Languages: English
• ISSNs: 1674-1137

Abstract

Abstract: SCAs (Switched Capacitor Arrays) have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents (±4 mA max) and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS (Mega-samples per Second) and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor.