Impact of technology scaling on analog and RF performance of SOI–TFET. (9th October 2015)

• Record Type: Journal Article
• Authors: Kumari, P; Dash, S; Mishra, G P
• Is Part Of: Advances in natural sciences. Volume 6:Number 4(2015)
• Publication Date: 2015-10-09
• Subjects: SOI–TFET -- tunneling path -- drain current -- intrinsic gate capacitance -- cut-off frequency; 2.01 -- 3.00 -- 3.02 -- 4.12; Nanotechnology -- Periodicals; Nanoscience -- Periodicals; 620.5
• DOI: 10.1088/2043-6262/6/4/045005
• Languages: English
• ISSNs: 2043-6254

Abstract

Abstract: This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD sentaurus device simulation results.