Study of high-tech process furnace using inherently safer design strategies (III) advanced thin film process and reduction of power consumption. (September 2016)

• Record Type: Journal Article
• Authors: Lu, Chih-Cheng; Chang, Kuo-Chi; Chen, Chun-Yu
• Is Part Of: Journal of loss prevention in the process industries. Volume 43(2016:Sep.)
• Page Start: 280
• Page End: 291
• Publication Date: 2016-09
• Subjects: Inherently safer design -- LPCVD -- Thin film deposition -- 22 nm IC process -- Reduction of power consumption -- FMEA; Chemical industries -- Safety measures -- Periodicals; 660.2804
• DOI: 10.1016/j.jlp.2016.05.030
• Languages: English
• ISSNs: 0950-4230

Abstract

Abstract: Semiconductor manufacturing is the economic backbone of Taiwan. Although efforts have been made to improve production capacity and achieve full load production, manufacturers are still unable to effectively control the power consumption situation during the failure of full load production due to special circumstances. Those processes do not conform to the characteristics of inherently safer design, which increases process risks. The objective of this research was to investigate the effects of power consumption reduction on the process furnace, maintaining the same production capacity in the existing 22 nm advanced semiconductor process. In this study, TEOS was used as the raw material for LPCVD process simulation, experimentation, and exploration. The adopted LPCVD reactor was of the commercial batch type; the process experiments simulated the IPD process applied on the 22 nm MOSFET, with a thickness of 5000 Å and process time of 60 min. The simulation results of different batches were compared with the experimental values, and the simulation values were consistent with the experimental values by adjusting the different ka values. The reactor contained processes for 125 wafers and 100 wafers. According to the simulation and experimental results, the thin film deposition results were acceptable. Finally, the heating zone output current was explored specifically for two batches of wafers in the 12″ furnace tube process. In the process of the first batch, as there were only 100 wafers, 18.05 A was reduced by shutting off the 5th heating zone. The machine had a voltage of 220 V and converted power output up to 3971 W, accounting for 26% (15265.8 W) of the entire machine. This significantly reduced power supply of the entire machine and hazard potential, which is consistent with the characteristics of inherently safer design. Moreover, there were fifteen 12″ tube furnace machines in the experimental workshop of this study, and shutting off unnecessary heating zones could reduce 59565 W/H of the power supply and hazard potential. Finally, the 12″ tube film process machine electrical hazards and damage control measures were analyzed by using FMEA method, and confirmed that the research results were in line with the expected attenuation strategy of ISD. This approach has increased the safety level, but also reduced operating costs, which is an important achievement of this study. Highlights: Summarized the current 22 nm advanced semiconductor process and integration design of element processes. Conducted hazard analysis of current 22 nm advanced semiconductor process, tools, and facility by using FMEA. Proposed the CVD thin film deposition of TEOS (tetraethyl orthosilicate) process conditions. Proposed the IPD process applied on the 22 nm MOSFETs, with a thickness of 5000 Å and process time of 60 min. Reduction of power consumption satisfied the attenuation strategy of ISD and converted power output up to 3971 W.