Design of QCA based Programmable Logic Array using decoder. (September 2016)

• Record Type: Journal Article
• Authors: De, Debashis; Purkayastha, Tamoghna; Chattopadhyay, Tanay
• Is Part Of: Microelectronics journal. Volume 55(2016)
• Page Start: 92
• Page End: 107
• Publication Date: 2016-09
• Subjects: QCA -- Decoder -- PLA -- Interfacing -- Recursion -- Cell count -- Crossover; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.06.005
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder. Highlights: A novel design of XOR gate is proposed which is extended to design decoder. The 2×4 Decoder achieves 50% delay and 33% cell count reduction. Estimation for wire-crossing numbers for design extension is suggested. Finally a novel QCA based PLA is designed with the proposed 4×16 decoder. The PLA is utilized to design a 2-bit Full Adder.