VLSI design of an RSA encryption/decryption chip using systolic array based architecture. Issue 9 (1st September 2016)

• Record Type: Journal Article
• Authors: Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi
• Is Part Of: International journal of electronics. Volume 103:Issue 9(2016)
• Page Start: 1538
• Page End: 1549
• Publication Date: 2016-09-01
• Subjects: VLSI -- cryptology -- RSA -- 2048-bit -- systolic array; Electronics -- Periodicals; Electronic control -- Periodicals; 621.381
• DOI: 10.1080/00207217.2016.1138511
• Languages: English
• ISSNs: 0020-7217

Abstract

ABSTRACT: This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm 2 (4.58 × 4.58 mm 2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.