A timing controller embedded driver IC with 3.24‐Gbps eDP interface for chip‐on‐glass TFT‐LCD applications. Issue 5 (22nd May 2016)

• Record Type: Journal Article
• Authors: Kim, Tae‐Jin; Baek, Changhoon; Chun, Sengsub; Lee, Kil‐Hoon; Hwang, Jong‐Il; Kwon, Kyeonghwan; Kim, Yong‐Hun; Park, Hyun‐Sang; Shin, Youngmin; Ryu, Seong‐young; Lee, Jae‐Youl; Hwang, Gyoocheol; Kim, Gyeongnam
• Is Part Of: Journal of the Society for Information Display. Volume 24:Issue 5(2016)
• Page Start: 299
• Page End: 306
• Publication Date: 2016-05-22
• Subjects: high‐speed interface -- display interface -- timing controller embedded driver -- embedded display port; Information display systems -- Periodicals; 621.38154205
• DOI: 10.1002/jsid.446
• Languages: English
• ISSNs: 1071-0922

Abstract

Abstract : This paper presents a timing controller embedded driver (TED) IC with 3.24‐Gbps embedded display port (eDP), which is implemented using a 45‐nm high‐voltage CMOS process for the chip‐on‐glass (COG) TFT‐LCD applications. The proposed TED‐IC employs the input offset calibration scheme, the zero‐adjustable equalizer, and the phase locked loop‐based bang‐bang clock and data recovery to enhance the maximum data rate. Also, the proposed TED‐IC provides efficient power management by supporting advanced link power management feature of eDP standard v1.4. Additionally, the smart charge sharing is proposed to reduce the dynamic power consumption of output buffers. Measured result demonstrates the maximum data rate of 3.24 Gbps from a 1.1 V supply voltage with a 7.9‐inch QXGA 60‐Hz COG‐LCD prototype panel and 44% power saving from the display system. Abstract : This paper presents a timing controller embedded driver (TED) IC with 3.24‐Gbps embedded display port (eDP), which is implemented using a 45‐nm high‐voltage CMOS process for the chip‐on‐glass (COG) TFT‐LCD applications. Additionally, the smart charge sharing is proposed to reduce the dynamic power consumption of output buffers.