Design and Analysis of n:2n Reversible Decoder. Issue 2 (2nd July 2016)

• Record Type: Journal Article
• Authors: Saha, Anish Kumar; Sambyo, Koj; Bhunia, C.T.
• Is Part Of: IETE journal of education. Volume 57:Issue 2(2016)
• Page Start: 65
• Page End: 72
• Publication Date: 2016-07-02
• Subjects: CNOT gate -- Decoder_2n/4 -- Garbage output -- Merger_2n -- Quantum computing -- Reversible gate -- Toffoli gate; Electrical engineering -- Periodicals; Electronics -- Periodicals; Electrical engineering; Electronics; Periodicals; 621.381
• DOI: 10.1080/09747338.2016.1162672
• Languages: English
• ISSNs: 0970-1664

Abstract

ABSTRACT: Every irreversible circuit has a heat dissipation problem. Heat dissipation of any irreversible circuit depends on number of losses of information and the heat generates due to irreversibility is minimum of Joules per bit loss. In order to avoid heat dissipation, it is needed to build reversible circuits for reduction of loss of information. This paper proposes to design a reversible decoder. The proposed design of reversible decoders has a common pattern for different values of n . The proposed design is a nesting structure where higher order decoder uses lower order decoder's components. Basic quantum gates such as Toffoli gate, CNOT, and Pauli X gates are used in this design.