A Physics-Based Model of Double-Gate Tunnel FET for Circuit Simulation. Issue 3 (3rd May 2016)

• Record Type: Journal Article
• Authors: Narendiran, A.; Akhila, K.; Bindu, B.
• Is Part Of: IETE journal of research. Volume 62:Issue 3(2016)
• Page Start: 387
• Page End: 393
• Publication Date: 2016-05-03
• Subjects: Band-to-band tunnelling -- full adder -- low power -- sub-threshold slope -- tunnel FET -- VLSI circuits; Electronics -- Periodicals; Telecommunication -- Periodicals; Electronics; Telecommunication; Periodicals; 621.38
• DOI: 10.1080/03772063.2015.1082443
• Languages: English
• ISSNs: 0377-2063

Abstract

ABSTRACT: Tunnel FETs (TFETs) having better ON–OFF switching performance is an alternative nano-device that replaces MOSFET (metal oxide field effect transistor) in low-power VLSI (very large scale integration) circuits. The physics-based models of TFETs are essential to integrate with circuit simulators for design and optimization of TFET-based circuits. There is no built-in TFET model available in any commercial circuit simulators. This paper presents the development of an accurate physics-based model for double-gate TFET and its integration in Cadence circuit simulator SPECTRE. The model captures all device physics and is evaluated for various device parameters such as channel length, oxide thickness, and high-κ dielectrics and validated with results from TCAD (Technology Computer Aided Design) Sentaurus. The integrated model is used to develop digital libraries of logic gates and adders. These digital libraries can be used to design TFET-based VLSI circuits. This method of integration using physics-based model of TFET, compared to look-up table approach which is purely data-driven, gives flexibility to circuit designers to design TFET-based low-power circuits taking into account the dependence on bias, temperature, scaling, and other process parameters.