Optimal transistor sizing for maximum yield in variation‐aware standard cell design. (26th October 2015)

• Record Type: Journal Article
• Authors: Abbas, Zia; Olivieri, Mauro
• Is Part Of: International journal of circuit theory and applications. Volume 44:Number 7(2016:Jul.)
• Page Start: 1400
• Page End: 1424
• Publication Date: 2015-10-26
• Subjects: CMOS -- standard cell -- yield -- statistical variation -- Monte Carlo -- leakage; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2167
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: Process variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst‐case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits (PDKs). The approach is demonstrated for a 40 nm low‐power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [−40 °C, 125 °C] and supply voltage range [0.95 V, 1.05 V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis (SPICE)‐level Monte Carlo analysis confirmed the estimated yield of the obtained circuits. Copyright © 2015 John Wiley & Sons, Ltd. Abstract : In this paper, robust circuit sizing and yield improvement of CMOS digital standard cells considering leakage and delay performance are presented. The outcome of presented mathematical optimization show yield improvement from an initial 50% (on average) to 99.9%, and the circuits under test are robust against the statistical variations (both local and global) for the whole given temperature (−40 to 125 °C) and supply voltage (0.95 to 1.05 V) ranges.