Off-chip bus power minimization using serialization with cache-based encoding. (August 2016)

• Record Type: Journal Article
• Authors: Mohammad, Khader; Kabeer, Ahsan; Taha, Tarek M.; Owaida, Muhsen; Washha, Mahdi
• Is Part Of: Microelectronics journal. Volume 54(2016)
• Page Start: 138
• Page End: 149
• Publication Date: 2016-08
• Subjects: Memory data bus power -- Frequent value encoding -- Serialization -- On and off-chip data bus minimization; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.06.002
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The data bus is a major component of high power consumption in small process high-performance systems and in systems-on-chip (SoC) design. This paper presents an analysis of different state-of-the-art techniques for reducing the power of off-chip memory bus interface, with proposing an approach overcoming some limitations existing in the state-of-art methods. More precisely, the paper introduces a serialization (S) method combined with cache-based encoding scheme, aiming at saving the optimal possible power for off-chip memory bus. Bus serialization reduces the number of transmission wires, while a Serialization-Widening (SW) approach reduces the bus capacitance and the number of transmission wires. Experimental results show that, for off-chip data bus, the serialization approach with cache-based encoding achieves 31% and 52% power reduction for single-core and multi-core applications, respectively, when using fixed voltage and frequency with 128 bits data bus.