Performance Analysis of Modified SHA-3. (2016)

• Record Type: Journal Article
• Authors: Chandran, Nithin R.; Manuel, Ebin M.
• Is Part Of: Procedia technology. Volume 24(2016)
• Page Start: 904
• Page End: 910
• Publication Date: 2016
• Subjects: Cryptography -- Secure Hash Algorithm-3 -- FPGA -- Area reduction; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.05.168
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: Security services have become an inseparable feature of almost all digital transactions. A crucial module of these scheme isintegrity, which is performed using a cryptographic hash function. Secure Hash Algorithm can be an efficient hashing technique.SHA-3 is the most recent and efficient Secure Hash Algorithm. Keccak has been chosen as the official algorithm for SHA-3 in2012. In this paper we propose a modification on the design of Secure Hash Algorithm (SHA-3) on Xilinx Field ProgrammableGate Array (FPGA) device. In order to provide reliable architecture for this algorithm, a concurrent error tolerant scheme forSHA-3 is used. A system based on the combination of SHA-3 and error tolerant scheme is also described. Simulation resultsshows, an efficiency in area and delay of SHA-3 designs.