Area Efficient Low Power Modified Booth Multiplier for FIR Filter. (2016)

• Record Type: Journal Article
• Authors: Haridas, Greeshma; George, David Solomon
• Is Part Of: Procedia technology. Volume 24(2016)
• Page Start: 1163
• Page End: 1169
• Publication Date: 2016
• Subjects: FIR filter -- Modified booth multiplier -- Spanning tree adder; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.05.070
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: Finite impulse response (FIR) filters are extensively used in various digital signal processing applications such as digital audio, image processing, data transmission, biomedical etc. In some applications, the FIR filter circuit must be capable to operate at high sample rates, while in other applications, the FIR filter circuit must be a low power circuit operating at moderate sample rates. FIR filters design implementation consist a large number of multiplications, which leads to excessive area and power consumption. The topology of the multiplier circuit affects the resultant area and power consumption. In this paper a new area efficient low power FIR filter design is proposed using a spanning tree based modified Booth multiplier realized in direct form. An area efficient modified spanning tree adder is also proposed, which enhances the area efficiency of FIR filter. The design is implemented using Xilinx 14.2 ISE tools, Model Sim, programming in VHDL. For implementation of the FIR filter, MATLAB Simulink tool is employed to determine various filter coefficients.