FPGA Implementation of High Quality Random Number Generator Using LUT Based Shift Registers. (2016)

• Record Type: Journal Article
• Authors: Justin, Remya; Mathew, Binu K.; Abe, Susan
• Is Part Of: Procedia technology. Volume 24(2016)
• Page Start: 1155
• Page End: 1162
• Publication Date: 2016
• Subjects: Field Programmable Gate Array (FPGA) -- Look Up Table (LUT) -- Random Number Generator (RNG); Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.05.069
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: Random numbers are required for wide range of applications such as in encryption of data, testing and Monte-Carlo simulations. So, hardware implementation of random number generator is inevitable. FPGA Optimized RNGs are more efficient in terms of resource than software based RNGs. The LUT-SR RNG, a type of FPGA RNG in which LUTs are configured into shift registers with varying length. The existing work provides a midpoint between LUT-OPT RNG and LUT-FIFO RNG. In the enhancement work, we proposed modified LUT-SR RNG which provides more randomness, quality and minimum resource utilization than the existing LUT-SR generator. Inorder to improve the randomness quadratic residue method is employed. Linear Congruential Generator (LCG) algorithm, one of the oldest and well known algorithm is also used in modified LUT-SR RNG to enhance the performance. Here design was made by VHDL programming language by using Xilinx software.