Parallel Computation Using DSP Slices in FPGA. (2016)

• Record Type: Journal Article
• Authors: Unnikrishnan, K. Supriya; Madhavan, Sudheesh
• Is Part Of: Procedia technology. Volume 24(2016)
• Page Start: 1127
• Page End: 1134
• Publication Date: 2016
• Subjects: FPGA -- DSP -- Parallel Processing; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.05.064
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: The sophistication of applications and hunger for high quality digital data demands increase in the processing power. High performance signal processing is possible only though parallelism. At the same time, flexibility and scalability are the need of the hour due to dynamically changing standards and design up gradation. This paper describes an implementation of the computational framework using the DSP Slices in the FPGA. The customized instructions will provide the computation flexibility whereas specialized DSP macros in FPGA ensure high performance.