Design and Analysis of 8 Bit Parallel Prefix Comparators Using Constant Delay Logic. (2016)

• Record Type: Journal Article
• Authors: George, Amy Mariam; Chandran, G. Jyothish
• Is Part Of: Procedia technology. Volume 24(2016)
• Page Start: 1178
• Page End: 1185
• Publication Date: 2016
• Subjects: Constant Delay Logic -- Dynamic Logic -- Parallel Prefix Comparators -- Small Swing Dynamic Comparator; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.05.074
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: Parallel Prefix Radix 2 8 bit Comparators using Constant Delay (CD) logic is presented in this paper. The constant delay logic pre discharges the output to zero logic and switches to a logic one through a critical path clocked PMOS transistor. CD logic operation is much faster than a dynamic logic circuit during its D-Q mode of operation. The comparator's architecture consists of two stages; where the first stage uses a pass transistor pre encoding circuitry for achieving low power consumption and the second stage employs a high performance dynamic-CD-static logic manner combination comparators. Design and simulation were carried out in Mentor Graphics ELDO Simulator using 180 nm technology.