A 15-fJ/conversion-step 0.4-V 100-kS/s rail- to-rail 10-bit SARADC. Issue 2 (2nd April 2016) - Roshani, Saeed; Salimpour, Navid; Mohamadpour, Golshan
Abstract : In this paper, a novel ultra-low-power 10-bit successive approximately register analogue to digital converter (SARADC) in 90 nm CMOS is presented. The proposed SARADC works on the 100 kHz frequency, which is desired for wireless sensor network applications. In this frequency, the comparator is the major power consuming unit of the ADC. Therefore, to realise the ultra-low-power ADC design, the ultra-low-power comparator is necessary. Using forward body-biasing method on the comparator results in significant reduction in ADC power consumption. The proposed ADC can operate at 0.4 V supply voltage, demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. An energy consumption of 15 fJ per sample was achieved using forward body-biasing method in successive approximation architecture. The proposed SARADC consumes only 1.1 µw at 0.4 V supply voltage, which features very good specification for low power applications.