Low-power multi-standard Viterbi decoder for wireless communication applications. Issue 2 (2nd April 2016)

• Record Type: Journal Article
• Authors: Yu, Chu; Lin, Bor-Shing; Cheng, Po-Hsun; Su, Yu-Shan
• Is Part Of: International journal of electronics letters. Volume 4:Issue 2(2016)
• Page Start: 228
• Page End: 238
• Publication Date: 2016-04-02
• Subjects: multi-standard -- error-correcting code -- soft decision -- wireless communication -- Viterbi decoder; Electronics -- Periodicals; Electronics; Periodicals; 621.38105
• DOI: 10.1080/21681724.2015.1028472
• Languages: English
• ISSNs: 2168-1732

Abstract

Abstract : A Viterbi code is a type of the well-known error correcting code (ECC), which provides a robust error control methodology for wireless communication systems. It can efficiently reduce the bit error rate of the receiver and hence the reliability of the receiver is improved at data fidelity. This paper presents a novel low-power Viterbi decoder (VD) with a four-bit soft decision. To provide a multi-standard ECC processor, this study proposes a code rate 1/2 and 1/3 of VD used in software-defined radio systems for the hardware accelerator. Based on the proposed Viterbi decoding scheme, the survivor memory can be eliminated totally. This scheme achieves energy savings of approximately 50% of the total power dissipation and obtains a lower latency than that of most classical VDs. Furthermore, to avoid overflow occurrences in the add-compare-select unit (ACSU), a normalised mechanism is proposed, which only uses simple shifters and selection operations to reduce the design complexity. Finally, because it is designed with a 0.18 μm complementary metal-oxide-semiconductor technology, the proposed chip uses approximately 26.2 K gates, and its power consumption is approximately 11 mW at 73 MHz.