Performance optimization of 1T-1C DRAMs: A quantitative study. (June 2016)

• Record Type: Journal Article
• Authors: Sharroush, Sherif M.
• Is Part Of: Microelectronics journal. Volume 52(2016)
• Page Start: 147
• Page End: 164
• Publication Date: 2016-06
• Subjects: 1T-1C DRAM -- Area -- Power consumption -- Quantitative analysis -- Read-cycle time -- Sense margin -- Write-cycle time; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.03.015
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: There is no doubt that the one-transistor one-capacitor dynamic random-access memories (1T-1C DRAMs) play the most important role as the main memory in several volatile storage systems. The performance of this type of memories is dependent to a large extent on the size of the cell-storage capacitor, C s, the bitline-parasitic capacitance, C BL, and the bitline precharge level, V pre . In this paper, the performance of such memories will be evaluated by a proposed figure of merit ( FOM ) that takes into account the area, the sense margin, the average power consumption, and the average cycle time in the entire memory chip. A quantitative analysis will be performed in order to derive a compact form for the proposed figure of merit. This figure of merit will be evaluated for a certain technology and for certain ranges of V pre, C s, and C BL with the optimum values of these parameters determined. The impact of technology scaling on the performance of the 1T-1C DRAM will also be investigated. The derived expressions for the read-access time and the power consumption will be compared with the simulation results for the 45 nm CMOS technology with V DD =1 V.