Analytical study, performance optimisation and design rules for customary static and dynamic subthreshold MOS translinear topologies. (July 2016)
- Record Type:
- Journal Article
- Title:
- Analytical study, performance optimisation and design rules for customary static and dynamic subthreshold MOS translinear topologies. (July 2016)
- Main Title:
- Analytical study, performance optimisation and design rules for customary static and dynamic subthreshold MOS translinear topologies
- Authors:
- Papadimitriou, Konstantinos I.
Houssein, Alexandros
Drakakis, Emmanuel M. - Abstract:
- Abstract: This paper aims to provide qualitative and quantitative answers to questions related to the impact of transistor-level design parameters upon the performance and accuracy of static and dynamic translinear (TL) circuits in subthreshold CMOS. A methodical, step-by-step, symbolic analysis, exploiting a simplified EKV-based approximation is performed upon customary static TL topologies, including the four MOS transistor (MOST) multiplier/divider, the squarer circuit and the alternating formation of a six MOST multiplier/divider. The logarithmic integrator is treated as a typical dynamic TL analysis example. The produced EKV-based symbolic analysis results are compared against the ideally expected behaviours and Spectre ® - BSIM 3 V 3 m o d e l - s i m u l a t i o n s . The satisfying agreement between the proposed EKV-based model and Spectre simulator allowed us to proceed further and investigate the conditions under which optimal behaviour is achieved. Optimisation techniques, based on MOSTs' geometrical parameters combinations, resulted in the articulation of practical design rules. Abstract : Graphical abstract: Abstract : Highlights: Study of the impact of transistor-level design parameters upon translinear circuits. Articulation of design rules for the analysis/synthesis of translinear circuits. Symbolic representation of the functionality of indicative translinear topologies. Articulation of a more detailed translinear Principle for subthreshold MOSFETS.
- Is Part Of:
- Microelectronics journal. Volume 53(2016)
- Journal:
- Microelectronics journal
- Issue:
- Volume 53(2016)
- Issue Display:
- Volume 53, Issue 2016 (2016)
- Year:
- 2016
- Volume:
- 53
- Issue:
- 2016
- Issue Sort Value:
- 2016-0053-2016-0000
- Page Start:
- 177
- Page End:
- 193
- Publication Date:
- 2016-07
- Subjects:
- EKV model -- Log-domain circuits -- Optimisation -- Subthreshold MOSFETs -- Translinear circuits
Microelectronics -- Periodicals
Microélectronique -- Périodiques
Microelectronics
Electronic journals
Journals - contents and abstracts
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621.3805 - Journal URLs:
- http://catalog.hathitrust.org/api/volumes/oclc/5877621.html ↗
http://www.sciencedirect.com/science/journal/00262692 ↗
http://www.intute.ac.uk/sciences/cgi-bin/fullrecord.pl?handle=lesa.1012319367 ↗
http://www.elsevier.com/journals ↗
http://www.elsevier.com/homepage/elecserv.htt ↗ - DOI:
- 10.1016/j.mejo.2016.04.007 ↗
- Languages:
- English
- ISSNs:
- 0959-8324
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 5758.973000
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 1366.xml