Design and analysis of a current mode integrated CTLE with charge mode adaptation. (July 2016) - Duvvuri, Divya; Pasupureddi, Vijaya Sankara Rao
Abstract: With the reduction in feature size of CMOS transistors, the off-chip link speeds have not increased in the same pace as the on-chip link speeds. This gap in speed demands for better interface circuitry to mitigate the adverse effects of the off-chip links, especially, the intersymbol interference due to limited channel bandwidth and reflections due to impedance discontinuities. In this work, a first current mode continuous time linear equalizer (CTLE) with charge mode pole-zero adaptation scheme is proposed. The proposed equalizer is realized with common gate (CG) topology using switched capacitor based pole-zero adaptation to suit varying channel characteristics. The input impedance of the CG-CTLE is made equal to the characteristic impedance of the off-chip link, eliminating the need for a separate resistive termination. Since the proposed CG-CTLE acts as the first stage of the current mode receiver, there is no need for a separate trans-impedance amplifier or a preamplifier. In addition, the proposed CG-CTLE is analytically compared with conventional common source (CS) CTLE for the same targeted output signal swing and power consumption. The CG-CTLE outperforms CS-CTLE in terms of bandwidth and SNR, and is supported by analysis and simulations. The proposed CG-CTLE is implemented in a 1.1 V, 65-nm CMOS technology. The performance results show that it achieves a data rate of 15 Gb/s while equalizing the loss of a 7.5 inch FR4 PCB trace. It also offers an input impedance of 44.6 Ω, SNR of 23 dB and a bandwidth of 7.575 GHz and consumes a power of 13.9 mW.