ASAP7: A 7-nm finFET predictive process design kit. (July 2016)

• Record Type: Journal Article
• Authors: Clark, Lawrence T.; Vashishtha, Vinay; Shifren, Lucian; Gujja, Aditya; Sinha, Saurabh; Cline, Brian; Ramamurthy, Chandarasekaran; Yeric, Greg
• Is Part Of: Microelectronics journal. Volume 53(2016)
• Page Start: 105
• Page End: 115
• Publication Date: 2016-07
• Subjects: Predictive process design kit -- 7-nm technology -- Process scaling -- Extreme ultraviolet lithography -- Self-aligned multiple patterning -- Design rules; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.04.006
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any specific foundry. The initial version assumes EUV lithography for key layers, a decision based on its present near cost-effectiveness and resulting simpler layout rules. Non-EUV layers assume appropriate multiple patterning schemes, i.e., self-aligned quadruple patterning (SAQP), self-aligned double patterning (SADP) or litho-etch litho-etch (LELE), based on 193-nm optical immersion lithography. The specific design rule derivation is explained for key layers at the front end of line (FEOL), middle of line (MOL), and back end of line (BEOL) of the predictive process modeled. The MOL and BEOL DRC rules rely on estimation of time dependent dielectric breakdown requirements using layer alignments determined with projected machine to machine overlay assumptions, with significant guard-bands where possible. A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown. The PDK transistor electrical assumptions are also explained, as are the FEOL design rules, and the models include basic design corners. The transistor models support four threshold voltage ( Vth ) levels for both NMOS and PMOS transistors. Cadence Virtuoso technology files and associated schematic and layout editing, as well as netlisting are supported. DRC, LVS, and full parasitic extraction is enabled through Mentor Calibre decks.