Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits. (July 2016)

• Record Type: Journal Article
• Authors: Ebrahimi, Seyyed Ashkan; Reshadinezhad, Mohammad Reza; Bohlooli, Ali; Shahsavari, Mahyar
• Is Part Of: Microelectronics journal. Volume 53(2016)
• Page Start: 156
• Page End: 166
• Publication Date: 2016-07
• Subjects: 4-valued logic -- CNTFET-based MVL -- Quaternary FA -- Nanoelectronics; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.04.016
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A new voltage mode design is presented for quaternary logic using CNTFETs. This architecture with presentation of a new structure for voltage division can be applied on any four-valued logic implementation. To ensure the functionality of this promising proposed architecture, basic gates, half-adder, and full-adder are implemented using voltage divider. Moreover, a decoder is considered to enhance the parameters of half-adder such as power consumption, delay, and number of transistors. The designs are simulated using Hspice simulation tool. In comparison with prior works, our half-adder design is optimized by 75.2%, 7.8% and 77% in power consumption, delay and PDP parameters, respectively.