A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS. (17th June 2016)

• Record Type: Journal Article
• Authors: Lv, Junsheng; Tian, Ze; Shao, Gang
• Is Part Of: IEEJ transactions on electrical and electronic engineering. Volume 11(2016:Jun.)Supplement 1
• Page Start: S101
• Page End: S107
• Publication Date: 2016-06-17
• Subjects: high‐speed serial links -- voltage mode -- transmitter; Electrical engineering -- Periodicals; Electronics -- Periodicals; 621.3
• DOI: 10.1002/tee.22242
• Languages: English
• ISSNs: 1931-4973

Abstract

Abstract : A low‐power low‐jitter voltage‐mode (VM) transmitter with two‐tap pre‐emphasis and impedance calibration for high‐speed serial links is presented. Based on a comprehensive analysis of the relationship between impedance, supply current, and pre‐emphasis of the output driver, an impedance control circuit (ICU) is presented to maintain the 50 Ω output impedance and suppress the reflection, a self‐biased regulator is proposed to regulate the power supply, and an edge driver is introduced to speed up the signal transition time. Therefore, the signal integrity (SI) of the transmitter is improved with low power consumption. The whole transmitter is implemented in 65‐nm CMOS technology. It provides an eye height greater than 688 mV at the far end with a root‐mean‐squared jitter of less than 6.99 ps at 5 Gbps. The transmitter consumes 15.2 mA and occupies only 370 μ m × 230 μ m. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.