Gate replacement with PMOS stacking for leakage reduction in VLSI circuits. (13th October 2015)

• Record Type: Journal Article
• Authors: Panwar, Uday; Khare, Kavita
• Is Part Of: International journal of numerical modelling. Volume 29:Number 4(2016:Jul./Aug.)
• Page Start: 565
• Page End: 576
• Publication Date: 2015-10-13
• Subjects: transistor stacking -- MLV -- IVC -- gate replacement -- leakage reduction -- WLS; Electric networks -- Mathematical models -- Periodicals; Electronics -- Mathematical models -- Periodicals; 621.3011
• DOI: 10.1002/jnm.2112
• Languages: English
• ISSNs: 0894-3370

Abstract

Summary: Scaling down the circuits of complementary metal oxide semiconductor increases the leakage current. Input vector control is an extremely popular method for controlling leakage without using any technological modification. However, it is less effective for larger logic depth circuits. Our study proposes a Worst Leakage State (WLS) free‐node algorithm based on gate replacement technique, in which, when the logic gate of a given circuit goes into WLS, it is replaced by a suitable variant of the gate which in turn reduces the leakage current in an idle mode of the circuit at the same input vector. These variants minimize leakage under WLS conditions. For replacement purpose, four variants (V1–V4) of a two‐input NAND gate are proposed. This technique is applied on different circuits and some benchmark circuits such as ISCAS'85 (C17) and ITC'99 (B01, B02 and B06) (total of 10 circuits), according to the proposed algorithm with variants V1–V4. The average total power is reduced to 15.04%, 15.04%, 35.7% and 31.5%, and the leakage current is reduced to 42.96%, 42.96%, 84.25% and 84.52%, respectively, for variants V1–V4. The average delay is decreased by 16.03% in V1 and V2 variants and increased by 7.74% and 13.16% for variants V3 and V4, respectively, as compared with the results of conventional circuits at 45‐nm Berkeley Predictive Technology Model technology. Copyright © 2015 John Wiley & Sons, Ltd.