Thermal and power aware task mapping on 3D Network on Chip. (April 2016)

• Record Type: Journal Article
• Authors: Mosayyebzadeh, Amin; Amiraski, Maziar Mehdizadeh; Hessabi, Shaahin
• Is Part Of: Computers & electrical engineering. Volume 51(2016)
• Page Start: 157
• Page End: 167
• Publication Date: 2016-04
• Subjects: NoC -- 3D NoC -- Task mapping -- Fuzzy logic; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2015.12.001
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: High integration and increased elements density in 3D Network on Chip (NoC) will cause more energy consumption and high temperature on chip. By mapping those tasks that have data communication between them to near cores, the communication delay and therefore, power consumption will be reduced. In addition, mapping the tasks to cores that are near the heat sink, in such a way that the generated heat is distributed indiscriminately all over the chip, will decrease maximum chip temperature. In this paper, we propose a task mapping method based on fuzzy logic that aims to alleviate power and thermal problems in 3D-NoCs. In this method, the weight of task mapping factors can be changed according to chip's requirements and therefore, we present a flexible and simple solution. Simulation results show reduction in average communication delay and power consumption, as well as substantial reduction in maximum core temperature.