A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS. Issue 4 (2nd June 2016)

• Record Type: Journal Article
• Authors: Ren, Xiaojiao; Zhuang, Yiqi; Li, Xiaoming; Qi, Zengwei; Wang, Bo
• Is Part Of: IEEJ transactions on electrical and electronic engineering. Volume 11:Issue 4(2016:Jul.)
• Page Start: 467
• Page End: 473
• Publication Date: 2016-06-02
• Subjects: successive approximation register analog‐to‐digital converter (SAR ADC) -- ultralow power -- switching sequence -- fully dynamic comparator -- bootstrapped switch -- CMOS; Electrical engineering -- Periodicals; Electronics -- Periodicals; 621.3
• DOI: 10.1002/tee.22263
• Languages: English
• ISSNs: 1931-4973

Abstract

Abstract : In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 C V ref 2 for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μ m EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.