MPI and UPC broadcast, scatter and gather algorithms in Xeon Phi. (28th May 2015)

• Record Type: Journal Article
• Authors: Mallón, Damián A.; Taboada, Guillermo L.; Koesterke, Lars
• Other Names: Silla Federico guestEditor.; Fröning Holger guestEditor.; Senger Hermes guestEditor.; Geyer Claudio guestEditor.
• Is Part Of: Concurrency and computation. Volume 28:Number 8(2016)
• Page Start: 2322
• Page End: 2340
• Publication Date: 2015-05-28
• Subjects: collective operations -- Xeon Phi -- manycore -- UPC -- MPI -- InfiniBand; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.3552
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Accelerators have revolutionised the high performance computing (HPC) community. Despite their advantages, their very specific programming models and limited communication capabilities have kept them in a supporting role of the main processors. With the introduction of Xeon Phi, this is no longer true, as it can be programmed as the main processor and has direct access to the InfiniBand network adapter. Collective operations play a key role in many HPC applications. Therefore, studying its behaviour in the context of manycore coprocessors has great importance. This work analyses the performance of different algorithms for broadcast, scatter and gather, in a large‐scale Xeon Phi supercomputer. The algorithms evaluated are those available in the reference message passing interface (MPI) implementation for Xeon Phi (Intel MPI), the default algorithm in an optimised MPI implementation (MVAPICH2‐MIC), and a new set of algorithms, developed by the authors of this work, designed with modern processors and new communication features in mind. The latter are implemented in Unified Parallel C (UPC), a partitioned global address space language, leveraging one‐sided communications, hierarchical trees and message pipelining. This study scales the experiments to 15360 cores in the Stampede supercomputer and compares the results to Xeon and hybrid Xeon + Xeon Phi experiments, with up to 19456 cores. Copyright © 2015 John Wiley & Sons, Ltd.