VLSI design of lossless frame recompression using multi-orientation prediction. Issue 1 (2nd January 2016)

• Record Type: Journal Article
• Authors: Lee, Yu-Hsuan; You, Yi-Lun; Chen, Yi-Guo
• Is Part Of: International journal of electronics. Volume 103:Issue 1(2016)
• Page Start: 14
• Page End: 29
• Publication Date: 2016-01-02
• Subjects: VLSI -- lossless frame recompression -- memory bandwidth -- video coding -- hardware architecture -- pipelining; Electronics -- Periodicals; Electronic control -- Periodicals; 621.381
• DOI: 10.1080/00207217.2015.1020885
• Languages: English
• ISSNs: 0020-7217

Abstract

Abstract : Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm 2 and 1.20 × 1.20 mm 2, respectively. Experiment results demonstrate that this work exhibits an outstanding performance on lossless compression ratio with a competitive hardware performance.