Toward reliable MIS‐ and MOS‐gate structures for GaN lateral power devices. Issue 4 (17th March 2016)

• Record Type: Journal Article
• Authors: Chen, Kevin J.; Yang, Shu; Liu, Shenghou; Liu, Cheng; Hua, Mengyuan
• Is Part Of: Physica status solidi. Volume 213:Issue 4(2016:Apr.)
• Page Start: 861
• Page End: 867
• Publication Date: 2016-03-17
• Subjects: GaN -- gate dielectrics -- interfaces -- metal–insulator–semiconductors structures -- power devices; Solid state physics -- Periodicals; Solids -- Industrial applications -- Periodicals; 530.41
• DOI: 10.1002/pssa.201532873
• Languages: English
• ISSNs: 1862-6300

Abstract

Abstract : GaN power switching transistors featuring MIS‐ and MOS‐gate structures are highly preferred over the Schottky‐gate counterpart, because of suppressed gate leakage, enlarged gate swing, and more scalable threshold voltage. Nevertheless, MIS‐/MOS‐gate GaN devices are confronted with stability and reliability challenges, which arise from interface traps at the critical dielectric/III‐nitride interface, as well as bulk traps inside the gate dielectric including border traps near the critical interface. In this work, we present several key techniques toward reliable MIS‐/MOS‐gate GaN power devices, including advanced interface engineering technology, gate structure optimizations for high‐performance/stability normally‐off GaN power transistors, and long‐lifetime gate dielectric technology. Schematic cross sections of GaN‐based MIS‐HEMT and MOS‐channel‐HEMT. Abstract : To realize highly reliable MIS‐ and MOS‐gate GaN power switching transistors, key techniques for the gate stack have been developed. By combining partial gate recess, fluorine ion implantation and nitridation interfacial layer, thermally stable normally‐off GaN transistors with low ON‐resistance are achieved. Gate dielectric grown by low‐pressure chemical vapor deposition at high temperature can significantly boost time‐dependent dielectric breakdown and prolong dielectric lifetime.