A RET-supported logic gate combinatorial library to enable modeling and implementation of intelligent logic functions. Issue 3 (9th December 2015)

• Record Type: Journal Article
• Authors: Gao, Ru-Ru; Shi, Shuo; Zhu, Ying; Huang, Hai-Liang; Yao, Tian-Ming
• Is Part Of: Chemical science. Volume 7:Issue 3(2016:Mar.)
• Page Start: 1853
• Page End: 1861
• Publication Date: 2015-12-09
• Subjects: Chemistry -- Periodicals; 540.5
• DOI: 10.1039/c5sc03570h
• Languages: English
• ISSNs: 2041-6520

Abstract

Abstract : A logic gate combinatorial library, including basic logic gates, a single three-input NOR gate, and combinatorial gates to realize intelligent logic functions (keypad-lock, parity checker) is constructed. Abstract : Boolean logic gates integrate multiple digital inputs into a digital output. Among these, logic gates based on nucleic acids have attracted a great deal of attention due to the prospect of controlling living systems in the way we control electronic computers. Herein, by employing Thioflavin T (ThT) as a signal transducer, we integrated multiple components based on RET (a type of proto-oncogene) into a logic gate combinatorial library, including basic logic gates (NOR, INHIBIT, IMPLICATION), a single three-input NOR gate, and combinatorial gates (INHIBIT–OR, NOT–AND–NOR). In this library, gates were connected in series where the output of the previous gate was the input for the next gate. Subsequently, by taking advantage of the library, some intelligent logic functions were realized. Expectedly, a biocomputing keypad-lock security system was designed by sequential logic operations. Moreover, a parity checker which can identify even numbers and odd numbers from natural numbers was established successfully. This work helps elucidate the design rules by which simple logic can be harnessed to produce diverse and complex calculations by rewiring communication between different gates. Together, our system may serve as a promising proof of principle that demonstrates increased computational complexity by linking multiple logic gates together.