Normally-off GaN-HEMTs with p-type gate: Off-state degradation, forward gate stress and ESD failure. (March 2016) - Meneghini, M.; Hilt, O.; Fleury, C.; Silvestri, R.; Capriotti, M.; Strasser, G.; Pogany, D.; Bahat-Treidel, E.; Brunner, F.; Knauer, A.; Würfl, J.; Rossetto, I.; et al.
Abstract: This paper reports an analysis of the degradation mechanisms of GaN-based normally-off transistors submitted to off-state stress, forward-gate operation and electrostatic discharges. The analysis was carried out on transistors with p-type gate, rated for 600 V operation, developed within the European Project HIPOSWITCH. DC measurements, thermal analysis by transient interferometric mapping (TIM), and transmission line pulse (TLP) were used in combination to achieve a complete description of the degradation and failure processes. The results of this investigation indicate that: (i) the analyzed devices have a breakdown voltage (measured at 1 mA/mm) higher than 600 V; in off-state, drain current originates from gate–drain leakage for drain voltages (VDS ) smaller than 500 V, and from vertical leakage through the conductive substrate for higher drain bias. (ii) step-stress experiments carried out in off-state conditions may induce instabilities in both drain–source conduction and gate leakage. Failure consists in the shortening of the gate junction, and occurs at VDS higher than 600 V. (iii) in forward bias, the p-type gate is stable up to 7 V; for higher gate voltages, a time-dependent degradation is detected, due to the high electric field across the AlGaN barrier; (iv) TIM analysis performed under short-circuited load conditions revealed hot spots at the drain side of the channel in the access region, thus indicating that these regions may behave as weak spots under high bias operation. Cumulative device degradation under such repeating pulses has also been revealed. (v) TLP tests were carried out to evaluate the voltage limits of the devices under off-state and on-state conditions. The results described within this paper provide relevant information on the reliability issues of state-of-the-art normally-off HEMTs with p-type gate. Highlights: First analysis of the degradation mechanisms of GaN-based normally-off transistors with p-type gate, submitted to off-state stress, forward-gate operation and electrostatic discharges DC measurements, thermal analysis by transient interferometric mapping (TIM), and transmission line pulse (TLP) were used in combination First analysis of the degradation under forward bias of the gate junction, based on dc and electroluminescence measurements TIM analysis performed under short-circuited load conditions revealed hot spots at the drain side of the channel in the access region TLP tests were carried out to evaluate the voltage limits of the devices under off-state and on-state conditions