An efficient multiple precision floating-point Multiply-Add Fused unit. (March 2016)

• Record Type: Journal Article
• Authors: Manolopoulos, K.; D. Reisis, ; Chouliaras, V.A.
• Is Part Of: Microelectronics journal. Volume 49(2016)
• Page Start: 10
• Page End: 18
• Publication Date: 2016-03
• Subjects: Floating-point -- Multiply-Add Fused -- Multiple precision -- VLSI; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.10.012
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Multiply-Add Fused (MAF) units play a key role in the processor׳s performance for a variety of applications. The objective of this paper is to present a multi-functional, multiple precision floating-point Multiply-Add Fused (MAF) unit. The proposed MAF is reconfigurable and able to execute a quadruple precision MAF instruction, or two double precision instructions, or four single precision instructions in parallel. The MAF architecture features a dual-path organization reducing the latency of the floating-point add (FADD) instruction and utilizes the minimum number of operating components to keep the area low. The proposed MAF design was implemented on a 65 nm silicon process achieving a maximum operating frequency of 293.5 MHz at 381 mW power.