Low power and robust memory circuits with asymmetrical ground gating. (February 2016)

• Record Type: Journal Article
• Authors: Jiao, Hailong; Qiu, Yongmin; Kursun, Volkan
• Is Part Of: Microelectronics journal. Volume 48(2016)
• Page Start: 109
• Page End: 119
• Publication Date: 2016-02
• Subjects: MTCMOS -- Data stability -- Static noise margin -- Write voltage margin -- Write assist transistor -- Leakage power consumption -- Data retention SLEEP mode -- Process parameter variations -- Minimum power supply voltage; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.11.009
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Multi-threshold CMOS (MTCMOS) technique is commonly used for suppressing leakage currents in idle circuits. The application of MTCMOS technique to static random access memory (SRAM) circuits is investigated in this paper. Two asymmetrically ground-gated MTCMOS SRAM circuits are presented for providing a low-leakage SLEEP mode with data retention capability. The read and hold static noise margins are increased by up to 7.24× and 2.39×, respectively, with the new asymmetrical SRAM cells as compared to conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. The overall electrical quality of a memory array is enhanced by up to 103.52× and 57.75% with the proposed asymmetrically ground-gated memory cells as compared to the conventional ground-gated 6T and eight-transistor (8T) SRAM cells, respectively. The new asymmetrical SRAM cells also exhibit enhanced tolerance to process parameter variations and lower minimum applicable power supply voltages as compared with the conventional 6T and 8T SRAM cells.