Input–output Rail-to-Rail CMOS CCII for low voltage–low power applications. (February 2016)

• Record Type: Journal Article
• Authors: Reda, Ahmed; Ibrahim, Mohamed F.; Farag, Fathi
• Is Part Of: Microelectronics journal. Volume 48(2016)
• Page Start: 60
• Page End: 75
• Publication Date: 2016-02
• Subjects: Rail-to-Rail CMOS CCII -- Constant trans-conductance gm -- OCEAN script language -- gm/ID characteristics -- Layout; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.12.001
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a novel circuit design for input–output Rail-to-Rail CMOS Second Generation Current Conveyor (CCII) for low voltage and low power applications. The designed circuit is structured from a single stage Rail-to-Rail Operational Amplifier (Op-Amp) and a conventional CMOS inverter as a class AB amplifier. Therefore, it provides a high wide range for input signal and high output current driving capability operation. In this paper, a new technique for an automated design script is created to produce a constant trans-conductance ( g m ) for the Rail-to-Rail Op-Amp using Open Command Environment (OCEAN) script language. The proposed Rail-to-Rail Op-Amp is based on a DC level shifter technique, which is cited at the input stage. This script allows the design problem to be cast as a program. Therefore, it offers an efficient, reliable, and fast way to implement high-performance of analog integrated circuits. Moreover, the physics-based g m / I D characteristic is used that is more suitable for short channel transistors in sub-micron processes. The circuit is simulated in IBM 0.13 µ CMOS technology with a single power supply 1.5-V. Virtuoso layout editor tool with caliber tools from Mentor Graphics are used to carry out the layout of the proposed circuit. The chip is fabricated by MOSIS Educational Program (MEP) and is tested to evaluate the performance of the proposed circuits. The measured and simulation results indicate a good agreement. Highlights: A novel circuit design for input–output Rail-to-Rail CMOS CCII for low voltage and low power applications is proposed. A new technique for an automated design script is created using Open Command Environment script language. The physics-based gm/ID characteristic is used that is more suitable for short channel transistors in sub-micron processes. Virtuoso layout editor tool with caliber tools from Mentor Graphics are used to carry out the layout. The chip is fabricated by MOSIS Educational Program.