BSIM4 parameter extraction for tri-gate Si nanowire transistors. (January 2016) - Tanaka, Chika; Saitoh, Masumi; Ota, Kensuke; Ishikawa, Takayuki; Numata, Toshinori
Abstract: We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes. SPICE modeling tool was used to extract the parameter from I d – V g to I d – V d characteristics with liner and saturation region. Dependence of source/drain parasitic resistances on nanowire width and gate sidewall thickness can be observed on the extracted parameters. Furthermore, parasitic capacitance was extracted from three-dimensional TCAD simulation with our fabricated device structure. Single sets of parameters can reproduce I – V characteristics with L g down to 35 nm for n -channel nanowire transistors. It was found that the extracted parameters will be a useful tool for characterizing the circuit performance of nanowire transistor. Therefore, this procedure is applicable to extract the BSIM4 model parameters for NW Tr. as well as other multi-gate FETs. Highlights: SPICE parameters of BSIM4 were successfully extracted for tri-gate NW Tr. Dependence of R sd on Tr. geometry and process can be observed on the parameter. Single sets of parameters for L g down to 35 nm were obtained. The parameters will be a useful tool for characterizing the circuit performance.