Analysis and optimization of the two-stage pipelined SAR ADCs. (January 2016)

• Record Type: Journal Article
• Authors: Shen, Yi; Zhu, Zhangming
• Is Part Of: Microelectronics journal. Volume 47(2016)
• Page Start: 40
• Page End: 44
• Publication Date: 2016-01
• Subjects: Pipelined SAR ADC -- MDAC -- Linearity -- High speed -- Optimization; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.10.018
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The two-stage pipelined SAR ADC (Successive Approximation Register Analog-to-Digital Convertor) is analyzed which consists of a SAR-based MDAC and a SAR ADC, with 1 bit redundancy to relax the requirement for the sub-ADC decision in accuracy. The stage resolution determines the performance of the ADC, which is optimized for high performance in linearity, noise, power, and speed. For the resolution of 10-bit, the optimal per stage resolution is about 5-bit in the first stage and 6-bit in the second stage. According to the analysis, a 10-bit two-stage pipelined SAR ADC was designed and fabricated in 180 nm CMOS, which achieves 56.04 dB SNDR and 5 mW power consumption from 1.8 V power supply at 50 MS/s.