Cite
HARVARD Citation
Wang, M. et al. (2016). A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations. Microelectronics journal. pp. 19-30. [Online].
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Wang, M. et al. (2016). A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations. Microelectronics journal. pp. 19-30. [Online].