Design and simulation of a parallel adaptive arbiter for maximum CPU utilization using multi-core processors. (October 2015)

• Record Type: Journal Article
• Authors: Akhtar, M. Nishat; Mohamad-Saleh, Junita; Sidek, Othman
• Is Part Of: Computers & electrical engineering. Volume 47(2015)
• Page Start: 51
• Page End: 68
• Publication Date: 2015-10
• Subjects: Parallel adaptive arbiter -- Multi-core -- CPU utilization -- System-on-Chip -- Bandwidth allocation; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2015.08.004
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: If we understand Moore's law and Amdahl's law then we can conclude that increasing number of CPU cores in a computing system is of no use just to attain high computation rate. We have designed a new arbitration technique which can use the CPU cores in a most optimised manner and can achieve high degree of task parallelism. The designed arbitration technique is superior to other existing arbitration technique in terms of CPU usage, bandwidth optimization and latency. The designed arbitration technique has been tested using high performance benchmark program to analyse its efficiency. Abstract: Parallelization of task is considered to be a huge challenge for future extreme-scale computing system. Sophisticated parallel computing system necessitates solving the bus contention in a most efficient manner with high computation rate. The major challenge to deal with is the achievement of high CPU core usage through increased task parallelism by keeping moderate bus bandwidth allocation. In order to tackle the aforesaid problems, a novel arbitration technique, known as Parallel Adaptive Arbitration (PAA) has been proposed for the masters designed according to the traffic behaviour of the data flow. These masters are implemented using a synthetic benchmark program that measures sustainable memory bandwidth and the corresponding computational rate. The proposed arbitration technique is a strong case in favour of fair bandwidth optimization and high CPU utilization, as it consumes the processor cores up to 77% through high degree of task parallelization and also reduces bandwidth fluctuation. Some of the works published so far in this area are reviewed, classified according to their objectives and presented in an organised manner with a conclusion. Graphical abstract: