Low power, high speed carbon nanotube FET based level shifters for multi-VDD Systems-On-Chips. Issue 12 (December 2015)

• Record Type: Journal Article
• Authors: Pasupathy, K.R.; Bindu, B.
• Is Part Of: Microelectronics journal. Volume 46:Issue 12 Part A (2015)
• Page Start: 1269
• Page End: 1274
• Publication Date: 2015-12
• Subjects: Carbon nanotube -- Level shifters -- Low power -- Optimization -- Power-delay product -- Systems-On-Chips; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.10.008
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Multi- V DD design reduces the power consumption in Systems-On-Chips (SoCs). As the level shifter in multi- V DD system imposes additional power consumption and propagation delay, it is necessary to optimize the level shifter circuit for minimum power-delay product (PDP) to obtain the potential benefit of using multiple power supply. Carbon nanotube FET (CNT-FET) is one of the novel devices that could replace conventional silicon MOSFET for low power applications due to its superior electrical properties. In this paper, the power and speed of CNT-FET based level shifters in 32-nm technology node are optimized by choosing chirality, diameter, number of nanotubes and substrate (back gate) bias for both feedback-based and multi- V TH based level shifters. While the increase in the number of nanotubes aids to increase the signal strength, the chirality and diameter can be used to set the threshold voltage of CNT-FETs. Using these parameters, the level shifters are optimized for PDP when it converts from 0.2 V to 0.9 V. The obtained minimum power-delay product of the chosen feedback-based level shifter (differential cascade voltage switch) is 0.522 aJ and that of multi- V TH based level shifter is 0.730 aJ. The PDP improvement for optimized CNT-FET based level shifter circuits is 6 times when compared to that of its silicon counterpart, FinFET based level shifters. This shows that the former can replace the latter for low power and high speed required for multi- V DD SoCs. Abstract : Highlights: The level shifter in multi- V DD system imposes additional power and delay. In this paper, the power and speed of CNT-FET based level shifters are optimized. The optimization is performed using number of nanotubes and back gate bias. CNT-FET based level shifter has PDP of 6 times lesser than FinFET based ones.