A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder. Issue 12 (December 2015)

• Record Type: Journal Article
• Authors: Katic, Nikola; Cojbasic, Radisav; Schmid, Alexandre; Leblebici, Yusuf
• Is Part Of: Microelectronics journal. Volume 46:Issue 12 Part A (2015)
• Page Start: 1343
• Page End: 1350
• Publication Date: 2015-12
• Subjects: Flash ADC -- Time-to-digital converter -- Fully-digital -- Pulse-based -- Time-domain; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.09.017
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The concept of time-domain reference-ladder for the implementation of fully-digital flash-ADCs is proposed in this work. The complete reference ladder is implemented using only digital circuits. Based on this concept, a flash ADC is proposed and implemented in this work using digital circuits, one comparator and a customized sample-and-ramp circuit. An unconventional time-to-digital conversion (TDC) technique is introduced which performs the complete conversion within a single clock cycle. The measurement results show that the proposed 5-bit converter achieves an 80 MHz sampling rate while consuming 900 μW of power from the 1.8 V supply voltage. The prototype ADC is developed in a 180 nm standard CMOS technology and achieves the power efficiency of 445 fJ/conversion which is comparable to many existing state-of-the-art flash ADCs. The measured performance is achieved without any design optimization or circuit calibration techniques confirming the promising benefits of the proposed topology. Thanks to the fully-digital structure, the circuit enables a robust and compact implementation which is very convenient for interleaving and beneficial for many potential applications.