A low-pass SPST switch in 65 nm CMOS. Issue 12 (December 2015) - He, Jin; Zhang, Yue Ping; Lim, Wei Meng; Xiong, Yong-Zhong
Abstract: A low-pass single-pole-single-throw (SPST) switch is analyzed and designed in a 1.2 V 65 nm bulk CMOS RF process for applications from DC to millimeter-wave frequencies. The SPST switch has a small active chip area of only 96 μm×140 μm and shows the measured wideband performance of insertion loss lower than 3 dB and isolation higher than 22 dB from DC to 70 GHz. In particular, it achieves 1.6 dB insertion loss, 27.9 dB isolation, and 14.5 dB return loss at 60 GHz. The SPST switch also shows the measured power-handling capability of 11.5 dBm at 40 GHz and simulated switching speed of 1 ns at 60 GHz. These results clearly demonstrate that the SPST switch has potential to be used in highly-integrated CMOS radios.