Online-Analysis of Hits in the Belle-II Pixeldetector for Separation of Slow Pions from Background. Issue 9 (December 2015) - Baehr, S; Sander, O; Heck, M; Pulvermacher, C; Feindt, M; Becker, J
Abstract: The impending Upgrade of the Belle experiment is expected to increase the generated data set by a factor of 50. This means that for the planned pixel detector, which is the closest to the interaction point, the data rates are going to increase to up to 28 Gbit/s. Combined with data generated by the other detectors, this rate is too big to efficiently send out to offline processing. In order to reduce the data rates online data reduction schemes, in which background is detected and rejected, are going to be employed. In this paper, an approach for efficient online data reduction for the planned pixel detector of Belle-II is presented. Its central part is the NeuroBayes algorithm, which is based on multivariate analysis. It allows the identification of signal and background by analyzing clusters of hits in the pixel detector on FPGAs. The algorithm is leveraging the fact that hits of signal particles can have very different characteristics, compared to background, when passing through the pixel detector. The applicability and advantages in performance are shown through the D* decay. In Belle-II, these decays produce pions with such a small transversal momentum, that they barely escape the pixel detector itself. In a common approach like an extrapolation of tracks from outer detectors to RoIs, these pions are simply lost, since they do not reach all necessary layers of the detector. However, cluster analysis is able to identify and separate these pions from the background, thus keeping their data. For that characteristics of corresponding hits, like the total amount of charge deposited in the pixels, are used for separation. The capability for effective data reduction is underlined by a background reduction of at least 90% and signal efficiency of 95%, for slow pions. An implementation of the algorithm for usage on Virtex-6 FPGAs that are used at the pixel detector was performed. It is shown that the resulting implementation succeeds in replicating the efficiency of the algorithm, implemented in software while throughputs that suffice hard real-time constraints, set by the read-out system of Belle-II, are achieved and efficient use of the resources present on the FPGA is made.