Design of low power and high read stability 8T-SRAM memory based on the modified Gate Diffusion Input (m-GDI) in 32 nm CNTFET technology. Issue 12 (December 2015)

• Record Type: Journal Article
• Authors: Abiri, Ebrahim; Darabi, Abdolreza
• Is Part Of: Microelectronics journal. Volume 46:Issue 12 Part A (2015)
• Page Start: 1351
• Page End: 1363
• Publication Date: 2015-12
• Subjects: Carbon Nanotube Field-Effect Transistor (CNTFET) -- Gate-Diffusion Input (GDI) technique -- Dynamic Threshold-Voltage (DT-MOSFET) technique -- Stack forcing technique -- P-CNTFET latch N-CNTFET access (PCLNCA) -- Static noise margin (SNM) -- N-Curve -- Stability-power dissipation ratio (SPR) -- Power-Delay-Product (PDP); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.09.016
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: SRAM designing with greater storage capacity and lower power dissipation with desired stability by employing conventional CMOS technology seems to be impossible due to enhancement of short channel effect and leakage current due to increasing the number of the transistors. Up to now a lot of methods have been proposed in order to improve the performance of the logical circuits based on the CMOS technology, among of them the Gate-Diffusion Input (GDI) technique is an efficient method. In this paper the modified GDI cell (m-GDI) based on the basic GDI cell is proposed and then SRAM cell memory with 8 transistors (8T-SRAM) which uses the proposed GDI cell is presented. Due to the achieved results the stability-power dissipation ratio (SPR), the evaluation parameter in SRAM memories, is improved about 7 for 8T-SRAM which is implemented with a stack forcing method in similar carbon nanotube field-effect transistor (CNTFET) technology. Finally the 4×4 SRAM memory is proposed based on 1×1 SRAM with the help of 8T-SRAM. This memory is presented with array structures for reading and writing blocks. The simulation results reveal that the Power-Delay Product (PDP) term decreases 18% and 36% in the reading and writing cycles respectively for the stack forcing SRAM with the same array. The simulation is done with H-SPICE software in 32 nm technology under the condition of 0.9 V supply voltage, 500 MHz frequency and room temperature.