A self-control technique for high efficiency class-E CMOS power amplifier. Issue 12 (December 2015)

• Record Type: Journal Article
• Authors: Dehqan, A.R.; Toofan, S.
• Is Part Of: Microelectronics journal. Volume 46:Issue 12 Part A (2015)
• Page Start: 1258
• Page End: 1262
• Publication Date: 2015-12
• Subjects: Class-E CMOS power amplifier -- Cascode topology -- Common-gate device -- Power loss; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.10.010
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, a self-control (SC) technique for high efficiency class-E CMOS power amplifier is presented for GSM standard. Cascode topology due to high sustainability of voltage stress is mostly considered in CMOS PAs, but slow transition of common-gate device from triode to cut-off region is the most problematic issue of cascode configuration and the main source of power loss. In order to minimize its power loss a positive feedback technique is used. The proposed technique speeds up on-to-off and off-to-on transition time and lower the on and off drain׳s voltage of the common-gate device. Therefore, the common-gate device turns off and on instantly after common-source device in lower drain voltage and consequently the technique shows an improvement in the overall performance of the PA. To demonstrate its performance a self-control class-E CMOS PA has been designed, simulate, and compared to conventional class-E CMOS PA. It has shown that more than 2% improvement is achieved in power-added efficiency (PAE). Under a 3.3 V power supply, the proposed CMOS PA in 0.18 um CMOS process at 1.8 GHz gives 29.6 dBm output power.