Electron energy distribution in Si/TiN and Si/Ru hybrid floating gates with hafnium oxide based insulators for charge trapping memory devices. Issue 2 (7th January 2016) - Cerbu, F.; Andreev, D. V.; Lisoni, J.; Breuil, L.; Afanas'ev, V. V.; Stesmans, A.; Houssa, M.
Abstract : Scaling the planar NAND flash cells to the 20 nm node and beyond mandates introduction of inter‐gate insulators with high dielectric constant ( κ ). However, because these insulators provide a smaller electron barrier at the interface with the poly‐Si floating gate, the program window and the retention properties of these scaled cells are jeopardized. To reduce the charge loss from the floating to the control gate, one may consider the introduction of a hybrid floating gate (HFG) structure comprised of poly‐Si and a high work function (WF) metal, e.g., TiN x ( x ∼ 1; WF ∼ 4.7 eV) or Ru (WF ∼ 5.3 eV). However, the very HFG concept is based on the assumption that electron trapping occurs inside the HFG stack rather than on traps present in the high‐ κ insulator. To examine this critical hypothesis, we analyzed the energy distribution of electrons trapped in flash cells with poly‐Si(2 nm)/TiN (6 nm)/Hf0.8 Al0.2 O x (19 nm, κ ∼ 15–19)/TiN x (10 nm) and Si(2 nm)/Ru (1 nm)/Hf0.8 Al0.2 O x (5 nm)/Al2 O3 (5 nm)/Hf0.8 Al0.2 O x (5 nm)/TiN x (10 nm) trapping gate stacks using the exhaustive photo‐depopulation spectroscopy. We found that trapped electron energy levels show a broad distribution (± 0.3 eV) centred at ∼3.2 eV below the oxide conduction band. The energy onset of electron de‐trapping at ∼2.8 eV matches the TiN x /HfO2 barrier height found from internal photoemission experiments, indicating that electrons are predominantly trapped inside the HFG.