Applying partial power-gating to bit-sliced network-on-chip. Issue 11 (November 2015)

• Record Type: Journal Article
• Authors: Wang, Feng; Tang, Xiantuo; Xing, Zuocheng
• Is Part Of: Microelectronics journal. Volume 46:Issue 11(2015)
• Page Start: 1002
• Page End: 1011
• Publication Date: 2015-11
• Subjects: Network-on-chip -- Bit-slicing -- Power-gating -- Low-power; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.09.001
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In the many-core systems, network-on-chip (NoC) serves as an efficient and scalable architecture to connect numerous on-chip resources, whereas it encounters the crisis of the increasing leakage power as technology is continually scaling down. Power-gating which is a representative low-power technique can be utilized to mitigate the increasing leakage power, but the disconnection problem suffered in the conventional power-gated NoC may severely affect network performance. In this paper, we propose a novel partial power-gating approach to avoid the performance loss caused by the disconnection. Firstly, we utilize the asymmetrical bit-slicing scheme to split router into two slices. After the bit-slicing of router datapath, the wide slices can be switched off to save some leakage power by using partial power-gating, but all narrow slices should be kept in ever-active state to avoid the disconnection. Next, owing to the slicing of router datapath, we redefine the packet format for the packet׳s slicing and transferring, and present two essential conversion modules to achieve packet׳s slicing and reassembling. In the synthetic traffic simulation, our design gains considerable power-saving at low-load and exhibits better performance behavior than the conventional power-gated design. The application simulation shows that our design can averagely save 27.5% of total power compared with the baseline design, and reduce 45.0% packet latency on average when compared with the conventional power-gated design. On balance, the bit-sliced NoC with partial power-gating has a better tradeoff between performance and power-efficiency. Abstract : Graphical abstract: We propose a novel partial power-gating approach to avoid the performance loss, and utilize the asymmetrical bit-slicing scheme to split router into two slices as shown inFig. 1 (a). The wide slices can be switched off to save some leakage power by using partial power-gating, but all narrow slices can be kept in ever-active state to avoid the disconnection as shown inFig. 1 (b). Bit-sliced NoC with partially power-gating. (a) Router. (b) Topology. Highlights: The asymmetrical bit-slicing scheme is utilized to slice router datapath. Power-gating is only applied to partial channel bits of each sliced router. Packet format is redefined to support the packet slicing. Two conversion modules are added to achieve packet's slicing and reassembling.