Exploring performance and power properties of modern multi‐core chips via simple machine models. (12th December 2013)

• Record Type: Journal Article
• Authors: Hager, Georg; Treibig, Jan; Habich, Johannes; Wellein, Gerhard
• Is Part Of: Concurrency and computation. Volume 28:Number 2(2016)
• Page Start: 189
• Page End: 210
• Publication Date: 2013-12-12
• Subjects: multi‐core -- power modeling -- performance modeling -- ECM model; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.3180
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Modern multi‐core chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution‐Cache‐Memory (ECM) model to describe the single‐core and multi‐core performance of streaming kernels. The model refines the well‐known roofline model, because it can predict the scaling and the saturation behavior of bandwidth‐limited loop kernels on a multi‐core chip. The saturation point is especially relevant for considerations of energy consumption. From power dissipation measurements of benchmark programs with vastly different requirements to the hardware, we derive a simple, phenomenological power model for the Sandy Bridge processor. Together with the ECM model, we are able to explain many peculiarities in the performance and power behavior of multi‐core processors and derive guidelines for energy‐efficient execution of parallel programs. Finally, we show that the ECM and power models can be successfully used to describe the scaling and power behavior of a lattice Boltzmann flow solver code. Copyright © 2013 John Wiley & Sons, Ltd.