STAC‐A2 on Intel architecture: evolving from scalar code to heterogeneous applications. (9th October 2015)

• Record Type: Journal Article
• Authors: Fiksman, Evgeny; Nikolaev, Andrey; Burylov, Ilya; Salahuddin, Sania
• Is Part Of: Concurrency and computation. Volume 28:Number 3(2016)
• Page Start: 878
• Page End: 891
• Publication Date: 2015-10-09
• Subjects: STAC‐A2 -- Intel Xeon Phi -- Intel® Threading Building Blocks (Intel® TBB) -- Intel® Math Kernel Library (Intel® MKL) -- Intel® VTune™ Amplifier XE -- OpenMP*; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.3691
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: STAC‐A2™ is a compute and memory intensive industry benchmark in the field of market risk analysis. The benchmark specifications were created by the Securities Technology Analysis Center (STAC®), and are based on the inputs collected from the leading trading companies, universities, and high performance computing vendors. The specifications describe models that represent realistic market risk analysis workloads. In this paper, we discuss the development steps that lead to the competitive performance of the STAC‐A2 benchmark executed on systems consisting of Intel® Xeon® processors and an Intel® Xeon Phi™ coprocessor. We show the importance of the utilization of all parallel resources available on Intel architectures to achieve maximum performance. We demonstrate that the offload extension supported by Intel® Composer XE minimizes the efforts required to create accelerated applications by using only C/C++ language. With Intel's latest implementation of the STAC‐A2 benchmark, we were able to achieve a significant (800%) performance gain by using a heterogeneous approach running on two Intel Xeon E5‐2699 v3 processors and a single Intel® Xeon Phi™ 7120A card, compared with earlier version running on only two Intel Xeon E5‐2697 v2 processors. Copyright © 2016 John Wiley & Sons, Ltd.