Optimized material solutions for advanced DRAM peripheral transistors (Phys. Status Solidi A 2∕2016). Issue 2 (11th February 2016)

• Record Type: Journal Article
• Authors: Spessot, Alessio; Ritzenthaler, Romain; Schram, Tom; Horiguchi, Naoto; Fazan, Pierre
• Is Part Of: Physica status solidi. Volume 213:Issue 2(2016:Feb.)
• Page Start: 484
• Page End: 484
• Publication Date: 2016-02-11
• Subjects: Solid state physics -- Periodicals; Solids -- Industrial applications -- Periodicals; 530.41
• DOI: 10.1002/pssa.201670610
• Languages: English
• ISSNs: 1862-6300

Abstract

Abstract : High‐ k dielectrics combined with metal gate (HKMG) represent the only way to meet the low leakage/high performance specifications for peripheral transistors required by the next‐generation nodes of DRAM. Significant performance improvement and internal operating voltage reduction can be achieved, combined with area scaling and overall cost reduction, in the area of the periphery surrounding the memory array (see image top‐left). Alessio Spessot et al. (pp.245–254 ) achieved significant development in the fabrication of transistors compatible with the stringent requirement of the DRAM memory array, including the fabrication of an innovative process flow which allows a very good effective Work Function (eWF) separation between NMOS and PMOS, as a function of diffusion anneal temperature. The process flow is described in the right panel of the cover page; and in the diagram bottom‐left, the maximum achievable eWF is shown. Optimized junction and thermally stable NiPt silicide fabrication, all compatible with the DRAM requirements, complete the obtained device tuning.