Optimized material solutions for advanced DRAM peripheral transistors. Issue 2 (2nd February 2016)

• Record Type: Journal Article
• Authors: Spessot, Alessio; Ritzenthaler, Romain; Schram, Tom; Horiguchi, Naoto; Fazan, Pierre
• Is Part Of: Physica status solidi. Volume 213:Issue 2(2016:Feb.)
• Page Start: 245
• Page End: 254
• Publication Date: 2016-02-02
• Subjects: CMOS -- DRAM -- gate stacks -- high‐k/metal gate -- MOSFET; Solid state physics -- Periodicals; Solids -- Industrial applications -- Periodicals; 530.41
• DOI: 10.1002/pssa.201532791
• Languages: English
• ISSNs: 1862-6300

Abstract

Abstract : The fabrication of peripheral CMOS devices for DRAM memories requires specific optimization with respect to a standard logic flow, imposed by the additional constraints linked to the memory element fabrication. Several process tunings are needed to keep pace with the request for low leakage and low cost devices combined with the needs of highly performant and resilient circuits. In this article, we summarize the most significant developments achieved in recent years focusing on HKMG Gate stack, junction tuning, silicide optimization for DRAM peripheral transistors. Three different solutions with different fabrication complexity and performance for HKMG, optimized junction, and thermally stable NiPt silicide fabrication, all compatible with the DRAM requirements, are discussed. Abstract : High‐ k dielectrics combined with metal gate (HKMG) represent the only way to meet the low leakage/high performance specifications for peripheral transistors required by the next generation nodes of DRAM and emerging memories. Significant performance improvement and internal operating voltage reduction can be achieved, combined with area scaling and overall cost reduction. The authors have developed multiple process flows for planar peripheral transistors, according to different customer needs.